This invention relates to a sample-and-hold device comprising
a series arrangement of a first and a second integrating circuit, each comprising an input, an output and a control signal input, the output of the first integrating circuit being coupled to the input of the second integrating circuit, PA0 a control unit for supplying a first and a second control signal to a first and a second output respectively, which first and second output are coupled to the control signal input of the first and the second integrating circuit respectively, and for supplying the first and the second control signal to the first and the second integrating circuit respectively. PA0 the output of the second integrating circuit is fed back to the input of the first integrating circuit, PA0 the first integrating circuit is controlled by said first control signal in a manner such that in said first integrating circuit an integration step is performed upon the difference between the input voltage at the input of the first integrating circuit and the output voltage fed back from the output of the second integrating circuit, and PA0 the second integrating circuit is controlled by said second control signal in a manner such that in said second integrating circuit, upon completion of the integration step in the first integrating circuit, an integration step is performed upon the output signal of the first integrating circuit.
Such a sample-and-hold device is described in, for example, German Offenlegungsschrift 1,931,242. This prior-art device employs integrating circuits which should be capable of handling input signals which vary comparatively strongly.
In general, the integrating circuits in such a sample-and-hold device are realized by means of a buffer stage in combination with capacitive elements and switching means. If these buffer stages are required to handle input signals which may vary within a large range, as is the case in the above-mentioned German Offenlegungsschrift 1,931,242, this may generally give rise to a comparatively strong signal distortion. Moreover, in general the limited common-mode input range of the buffer stage will impose a limitation on the permissible signal swing. This applies in particular, though not exclusively, to CMOS circuits.